An efficient high-speed block turbo code decoding algorithm and hardware architecture design

We propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo codes (BTCs) support variable code rates and packet sizes, and show a high-performance owing to a soft decision iterative decoding of turbo codes. However, BTCs have a long decoding time because of an iterative decoding and complicated extrinsic information operation. The proposed algorithm, using the threshold that represents channel information, reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of an LLR (log likelihood ratio) in consideration that the LLR distribution is Gaussian. As a result of logic synthesis using 0.35 μm CMOS technology, it is proved that the decoder applied by the proposed algorithm reduces the decoding time by about 30% and includes about 20K logic gates and 32 Kbit memory size.