Title :
A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching
Author :
Shoji, K. ; Moniwa, M. ; Yamashita, H. ; Kisu, T. ; Kaga, T. ; Torri, K. ; Kumihashi, T. ; Morimoto, T. ; Kawakami, H. ; Gotoh, Y. ; Itoga, T. ; Tanaka, T. ; Yokoyama, N. ; Kure, T. ; Ohkura, M. ; Fujisaki, Y. ; Sakata, K. ; Kimura, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.
Keywords :
DRAM chips; cellular arrays; ferroelectric storage; integrated circuit metallisation; lead compounds; masks; passivation; piezoceramics; platinum; sputter etching; titanium compounds; -2.5 to 2.5 V; 0.5 micron; 4 Kbit; Pt-PZT-Pt-TiN; Pt-PbZrO3TiO3-Pt-TiN; automatic nonvolatile writing; cell area; ferroelectric memory cell; ferroelectric write/read; metallization; nonseparated plate electrode; nonvolatile DRAM cell; one-mask dry etching; passivation; Capacitors; Dry etching; Electrodes; Ferroelectric materials; Metallization; Nonvolatile memory; Planarization; Plugs; Random access memory; Writing;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507781
