DocumentCode :
2127097
Title :
Copper interconnection deposition techniques and integration
Author :
Gang Bai ; Chien Chiang ; Cox, N. ; Sychyi Fang ; Gardner, D.S. ; Mack, A. ; Marieb, T. ; Xiao-Chun Mu ; Ochoa, V. ; Villasol, R. ; Jick Yu
Author_Institution :
Components Res., Intel Corp., Santa Clara, CA, USA
fYear :
1996
fDate :
11-13 June 1996
Firstpage :
48
Lastpage :
49
Abstract :
Copper has been deposited into prepatterned high-aspect-ratio (3:1) trenches using electroplating (EP), CVD and sputter reflow. Filling capability, electrical properties, electromigration lifetimes and mechanical stress are examined. Also, barriers against Cu diffusion are studied using electrical bias at elevated temperatures. CVD Cu can fill high aspect ratio features that electroplating cannot. Sputter-reflowed Cu can also fill high aspect ratio features, but has a high thermal budget for features >0.4 /spl mu/m. Preliminary results show that CVD Cu may be limited by electromigration lifetime.
Keywords :
chemical vapour deposition; copper; diffusion barriers; electromigration; electroplating; integrated circuit interconnections; internal stresses; sputter deposition; CVD; Cu; copper interconnection; deposition technique; diffusion barrier; electrical properties; electromigration lifetime; electroplating; filling capability; integration; mechanical stress; prepatterned high-aspect-ratio trench; sputter reflow; Copper; Electromigration; Filling; Mechanical factors; Stress; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
Type :
conf
DOI :
10.1109/VLSIT.1996.507789
Filename :
507789
Link To Document :
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