The effect of intrinsic capacitance degradation on circuit performance

The effects of intrinsic capacitance degradation in deep submicron CMOS technology are investigated. This investigation shows that: the measured C/sub gd/ decreases while C/sub gs/ increases during the accelerated hot-carrier stress with V/sub ds//spl Gt/V/sub gs/>V/sub th/; the simulated degraded circuit performance is improved by inclusion of C/sub gd/ degradation over just including I/sub dsat/ degradation; the inclusion of intrinsic capacitance degradation into performance analysis may be critical to the derivation of realistic hot-carrier reliability evaluation.