Title :
A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures
Author :
Si, Ruihao ; Li, Fule ; Zhang, Chun
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18μm technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds.
Keywords :
analogue-digital conversion; counting circuits; voltage-controlled oscillators; OPAMP-based ADC architecture; UMC 0.18um technology; VCO-based ADC architecture; frequency 1.037 GHz; hold circuit; input signal; multi phase edge counter; multi phase ring oscillator; output resolution; power consumption; quantization process; size 0.18 mum; time interleaved ADC architecture; wideband input; word length 7 bit; Capacitance; Clocks; Computer architecture; Delay; Ring oscillators; Transistors; Voltage-controlled oscillators; Multi phase ring oscillator; Quantization; Sample and hold clock; Time interleaved ADC; VCO-based ADC;
Conference_Titel :
Consumer Electronics, Communications and Networks (CECNet), 2012 2nd International Conference on
Conference_Location :
Yichang
Print_ISBN :
978-1-4577-1414-6
DOI :
10.1109/CECNet.2012.6202063
