Title :
Highly robust 0.25-/spl mu/m single-poly-gate CMOS with inter-well deep trenches
Author :
Inokawa, H. ; Okazaki, Y. ; Nishimura, K. ; Date, S. ; Ishihara, T. ; Mizusawa, T. ; Miyake, M. ; Kobayashi, T. ; Tsuchiya, T.
Author_Institution :
NIT LSI Labs., Kanagawa, Japan
Abstract :
An advanced buried channel PMOS was precisely compared with a surface channel counterpart, and it was shown to maintain advantages for the 0.25-/spl mu/m generation. 0.25-/spl mu/m single-poly-gate CMOS combined with deep-trench inter-well isolation showed high robustness to latchup, soft errors and ESD, and attained a 1.8/spl times/ speed performance improvement relative to 0.5-/spl mu/m CMOS in a typical logic gate and a 48/spl times/48-bit multiplier.
Keywords :
CMOS integrated circuits; integrated circuit technology; isolation technology; 0.25 micron; ESD immunity; Si; buried channel PMOS; inter-well deep trenches; latchup immunity; single-poly-gate CMOS process; soft error immunity; trench inter-well isolation; CMOS logic circuits; Electrostatic discharge; Logic gates; Robustness;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507856
