Title :
New improved 1-bit full adder cells
Author :
Veeramachaneni, Sreehari ; Srinivas, M.B.
Author_Institution :
Centre for VLSI & Embedded Syst. Technol. (CVEST), Int. Inst. of Inf. Technol., Hyderabad
Abstract :
The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.
Keywords :
adders; application specific integrated circuits; logic design; logic gates; low-power electronics; XNOR gates; XOR gates; application specific integrated circuits; delay; full adder cells; low transistor count; power consumption; Added delay; Adders; Application specific integrated circuits; CMOS logic circuits; Embedded system; Energy consumption; Equations; Information technology; Integrated circuit technology; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on
Conference_Location :
Niagara Falls, ON
Print_ISBN :
978-1-4244-1642-4
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2008.4564632
