DocumentCode
2132287
Title
Buffer capacity analysis under the influence from timing jitter in SDH system
Author
Xiao-Ping, Yan ; Pei-Da, Ye
Author_Institution
Beijing Univ. of Posts & Telecommun., China
Volume
2
fYear
1996
fDate
5-7 May 1996
Firstpage
809
Abstract
The influence on the buffer capacity from timing jitter with different features has been analysed and the method of selection of the buffer capacity corresponding to a concrete communication system is proposed. Under multiple-sources of timing jitter, a stable result for the buffer capacity is given through the pointer adjustment process, bit accumulation in the buffer and and the jitter variations. This result shows that the buffer capacity can be reduced greatly compare to the conventional method
Keywords
buffer storage; jitter; synchronous digital hierarchy; SDH system; bit accumulation; buffer capacity analysis; communication system; jitter variation; multiple sources; pointer adjustment; timing jitter; Artificial intelligence; Clocks; Concrete; Density functional theory; Frequency synchronization; Power generation economics; Synchronous digital hierarchy; Timing jitter; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Technology Proceedings, 1996. ICCT'96., 1996 International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-2916-3
Type
conf
DOI
10.1109/ICCT.1996.545004
Filename
545004
Link To Document