Investigating an aggressive mode for drowsy cache cells

Applying an aggressive policy to a traditional drowsy cache block management is investigated, where each cache line is allowed to remain in low leakage, low voltage state as long as it is idle. Only for write and read operations, the normal high voltage is applied to the cache line. There is no need for extra cycles or extra control signals to awake the drowsy cache cell, before accessing it. Thus, the performance penalty associated with traditional drowsy caches is reduced. Furthermore, there is no need for complex control circuitry to estimate the best time when to put the cache cells into drowsy mode. Best of all, the aggressive drowsy mode can reduce the leakage power consumption more than the traditional drowsy according to the cache access rate and operating frequency.