Title :
Mechanism of hot electron trapping on PMOSFET with p/sup +/ polysilicon gate
Author :
Kato, I. ; Horie, H. ; Taguchi, M. ; Ishikawa, H.
Author_Institution :
Fujitsu Lab. Ltd., Atsugi, Japan
Abstract :
The hot-carrier effects of a p/sup +/ polysilicon PMOSFET are compared with those of a surface-channel-type n/sup +/ polysilicon-gate PMOSFET. The p/sup +/ and the n/sup +/ PMOSFETs are fabricated with the same process except for doping of the gate polysilicon. MOS capacitors with p/sup +/ or n/sup +/ polysilicon gates are also prepared. The p/sup +/ FET has a highly boron doped SiO/sub 2/ film. An FN (Fowler-Nordheim)-tunneling constant-current stress test of MOS capacitors and the drain avalanche hot-carrier stress-time dependence of the threshold voltage shift indicate that electrons are distributed near the p/sup +/ polysilicon/SiO/sub 2/ interface, while they are located uniformly in the SiO/sub 2/ film of an n/sup +/ polysilicon gate MOSFET.<>
Keywords :
hot carriers; insulated gate field effect transistors; Fowler-Nordheim tunneling; MOS capacitors; PMOSFET; SiO/sub 2/:B; constant-current stress test; hot electron trapping; hot-carrier effects; hot-carrier stress-time dependence; p/sup +/ polycrystalline Si-SiO/sub 2/; polysilicon gate MOSFET; surface channel; threshold voltage shift; Boron; Doping; Electron traps; FETs; Hot carrier effects; Hot carriers; MOS capacitors; MOSFET circuits; Stress; Testing;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32738
