DocumentCode :
2134445
Title :
VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems
Author :
Arioua, Mounir ; Belkouch, Said ; Agdad, Mohamed ; Hassani, Moha M´rabet
Author_Institution :
Dept. of Electr. Eng., Cadi Ayyad Univ., Marrakech, Morocco
fYear :
2011
fDate :
7-9 April 2011
Firstpage :
1
Lastpage :
5
Abstract :
The Fast Fourier Transform (FFT) and its inverse transform (IFFT) processor are key components in many communication systems. An optimized implementation of the 8-point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper. The butterfly - Processing Element (PE) used in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in one method and eliminates the multiplicative complexity by using add and shift operations in other proposed method. The pipeline architecture R2MDC has been implemented with the 8-point module and simulation results show that this module significantly achieves a better performance with lower resource usage.
Keywords :
OFDM modulation; computational complexity; fast Fourier transforms; hardware description languages; inverse transforms; pipeline arithmetic; radiocommunication; telecommunication computing; 8-point FFT processor; 8-point module; IFFT processor; OFDM systems; PE; R2MDC architecture; VHDL implementation; communication systems; fast Fourier transform; inverse transform processor; lower resource usage; multiplicative complexity; optimized implementation; pipeline architecture R2MDC; processing element; radix-2 algorithm; real constant multiplication; Cooley-Tukey; FFT/IFFT; OFDM; R2MDC; VHDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia Computing and Systems (ICMCS), 2011 International Conference on
Conference_Location :
Ouarzazate
ISSN :
Pending
Print_ISBN :
978-1-61284-730-6
Type :
conf
DOI :
10.1109/ICMCS.2011.5945661
Filename :
5945661
Link To Document :
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