An Ant Colony Optimization approach for test pattern generation

Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuous increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on ant colony optimization (ACO). The paper studies the opportunities offered by ACO in comparison with other simulated-based ATPGs. The method is implemented and is shown to efficiently generate a set of test vectors that achieve a high fault coverage in a short time. Several benchmark circuits are attempted, and favorable results comparisons are reported.