Future technology trends for static RAMS

Author

Flanagan, Shane

Author_Institution

Motorola Semicond. Products, Austin, TX, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

40

Lastpage

43

Abstract

SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance of interconnected limitations for circuit choices is discussed. CMOS and BiCMOS circuits are compared. Future packaging, chip size, electromigration, and signal-propagation constraints are treated. The major data-integrity issues (cell stability, data retention and soft-error) are examined for future scaled processes.<>

Keywords

BIMOS integrated circuits; CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; technological forecasting; BiCMOS circuits; CMOS; SRAMs; VLSI; cell stability; chip architecture; chip size; circuit choices; data retention; data-integrity issues; electromigration; future scaled processes; future technology trends; interconnected limitations; near future; packaging constraints; process requirements; scaling; signal-propagation constraints; soft-error; speed limits; static RAMS; static random access memory; technology constraints; BiCMOS integrated circuits; CMOS technology; Circuit stability; Electromigration; Integrated circuit interconnections; Packaging; Process design; Random access memory; Read-write memory; SRAM chips;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32745

Filename

32745