DocumentCode :
2136678
Title :
Design of highly parallel linear digital circuits based on symbol-level redundancy
Author :
Nakajima, Masami ; Kameyama, Michitaka
Author_Institution :
Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan
fYear :
1996
fDate :
29-31 May 1996
Firstpage :
104
Lastpage :
109
Abstract :
In the non-linear digital system, it is difficult to design systematically highly parallel digital circuits whose output digit depends on a small number of input digits. On the other hand, the concept of linearity in digital systems is very attractive because analytical methods can be utilized to design highly parallel circuits. One of the most important problems in the design is to transform an original specification to a linear one. The design method of highly parallel circuits based on a necessary condition has been discussed. However, we cannot always find the solution even if the necessary condition is satisfied. To solve the problem, a sufficient condition for linearity is derived. If the sufficient condition is satisfied, we can design the linear circuit from the specification by the use of multiplicated redundant symbols
Keywords :
computational complexity; digital circuits; multivalued logic circuits; highly parallel circuits design; highly parallel linear digital circuits; multiplicated redundant symbols; output digit; sufficient condition; symbol-level redundancy; Adders; Concurrent computing; Delay; Design methodology; Digital circuits; Digital systems; Integrated circuit interconnections; Linearity; Logic circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on
Conference_Location :
Santiago de Compostela
ISSN :
0195-623X
Print_ISBN :
0-8186-7392-3
Type :
conf
DOI :
10.1109/ISMVL.1996.508344
Filename :
508344
Link To Document :
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