Novel application-specific signal processing architectures for wideband CDMA and TDMA applications

A new class of flexible and efficient digital signal processing architectures is presented for use in the design of transceivers for 2.5G and 3G networks. We begin by first looking at the class of algorithms found in these systems, and analyze the algorithmic complexity. This is then followed by an evaluation of the computational complexity of various architectures to implement the required transceiver digital signal processing. We show, that by systematically analyzing the dataflow and control flow processes in these algorithms, critical information to generate an optimal architecture can be discovered. Then, the new class of architectures characterized as heterogeneous reconfigurable multiprocessors is presented. Their computational efficiency and cost are shown to be low in today´s CMOS VLSI technology, making them an ideal choice for realizing flexible digital transceivers for multimode- multiservice- multistandard network equipment. Examples are presented for wideband TDMA and CDMA systems