A CMOS implementation of a Connex memory

The Connex Memory was introduced as a physical support for efficient symbolic processing. CM allows a significant speed-up over conventional CAMs in applications such as string matching with don´t cares in time related to the size of the string, regardless the size of the CM content. This paper presents a parametrical implementation of an enhanced version of CM at algorithmic-level, as well as gate-level, using VHDL language and Cadence software package. The basic cell is dynamically implemented and the electric analysis is performed in the Mietec 2 μm technology. The behavior of all the other blocks is validated by logic simulation using the `leapfrog´ simulator from Cadence. Schemes, programs in VHDL and complexity issues are illustrated and discussed in the paper. In addition, applications of the CM are presented, including support for functional and logical programming, relational databases, DNA computing (splicing operation) and others