Title :
Development of multi stack package with high drop reliability by experimental and numerical methods
Author :
Shin, Dongkil ; Lee, DukYong ; Ahn, Eunchul ; Kim, Taehun ; Cho, Taeje
Author_Institution :
Memory Div., Samsung Electron. Co., Gyeonggi-Do
Abstract :
Board level drop reliability of MSP (multi stack package) composed of a logic chipset package at bottom and an MCP (multi chip package) at top was investigated. The reliability of the package was tested by a developed drop (shock) tester. Applied shock level was half sine shape with 1500 G peak acceleration and 0.5 msec duration time. Failures were detected by four daisy chain loops going through solder balls and traces on each package. All failures were observed at the bottom chipset solder ball. The locations of failed balls were observed by dye and pry technology. The detailed physics of failure was observed by cross sectioning. EDX analysis was carried out at the failed IMC (inter-metallic compound) layer and brittle fracture between Cu6 Sn5 and Cu3Sn was observed. Fluctuation of the test board was measured by an accelerometer, strain gage, and gap sensor. A modal test was performed to measure the natural frequency of the board. Complex phenomena during the short period of the drop were analyzed by numerical simulation; finite element method. A simplified beam and shell model was adopted to obtain the global motion of the board, and a three-dimensional continuum sub model was adopted for the detail analysis of the ball. Both axial force and bending moment on the solder were good failure parameters. Local stress analysis showed stress concentration at the edge of a solder ball. Modal dynamic analysis gave similar result to real time analysis and its computation time was 1/6 of implicit analysis
Keywords :
chip scale packaging; copper alloys; failure analysis; finite element analysis; multichip modules; reliability; tin alloys; 0.5 ms; Cu3Sn; Cu6Sn5; EDX analysis; IMC; MCP; MSP; axial force; bending moment; board level drop reliability; brittle fracture; chipset solder ball; daisy chain loops; failure detection; finite element method; high drop reliability; implicit analysis; inter-metallic compound layer; local stress analysis; logic chipset package; modal dynamic analysis; multichip package; multistack package; numerical simulation; Acceleration; Electric shock; Logic; Packaging; Physics; Shape; Strain measurement; Stress; Testing; Tin;
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
Print_ISBN :
1-4244-0152-6
DOI :
10.1109/ECTC.2006.1645673