A power-performance scalable FPGA using configurable voltage domains and a design mapping tool

Power scaling in FPGA can be enabled with support for distributed configurable voltage domains and block-level control. Each configurable logic block (CLB) represents a unique power domain tile on the chip. Each tile can be configured independently to operate at high VDD, low VDD, or disabled. In this work, a customized design flow to support multiple on-chip voltage domains leverages existing commercial tools Astro and standard cell library enhanced with a few additional cells for power management. In this paper, the authors developed a power-aware place and route-tool to determine which non-critical paths can run at reduced voltage and to configure the various domains of the array accordingly. By introducing fine-grain hardware controls, power-aware FPGA forms the basis for a platform that allows for effective in-system energy delay tradeoffs for energy-constrained applications such as handheld wireless systems.