A method of automatically tuning gate length and width in a standard cell

This paper presents a method of tuning the gate length and width in a standard cell for reuse, which includes the algorithm for auto-identification, obtaining of the gate information and tuning of the locations and/or sizes of the related layout patterns. Existing layouts of standard cells are reused to design new standard cells. Experimental results show that this method can improve the efficiency of standard cell designs and facilitate the generation of standard cells satisfying the requirements of physical optimization.