Title :
Fully planarized 0.5 mu m technologies for 16-Mb DRAM
Author :
Wakamiya, W. ; Eimori, T. ; Ozaki, H. ; Itoh, H. ; Fujiwara, K. ; Shibano, T. ; Miyatake, H. ; Fujii, A. ; Tsutsumi, T. ; Satoh, S. ; Katoh, T.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The authors describe key points of 0.5- mu m technologies for fabricating high-density memory devices such as 16-Mb DRAM (dynamic random access memory). The main features of the technologies are the use of field-shield isolation and a W contact source/drain transistor utilizing silane reduction of WF/sub 6/. The field-shield isolation technology enables the isolation region to be reduced down to half a micron. The selective W deposition leads to a reduction of the parasitic resistance. A fully planarized T-shaped stacked capacitor cell was fabricated and found to be suitable for a 16-Mb DRAM.<>
Keywords :
VLSI; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; integrated memory circuits; metallisation; random-access storage; tungsten; 16-Mb DRAM; ULSI; dynamic random access memory; features; field-shield isolation; high-density memory devices; planarized T-shaped stacked capacitor cell; selective W deposition; Capacitors; DRAM chips; Isolation technology; Random access memory;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32802
