DocumentCode
2144123
Title
“Condition-based” dummy fill insertion method based on ECP and CMP predictive models
Author
Nitta, Izumi ; Kanazawa, Yuji ; Fukuda, Daisuke ; Shibuya, Toshiyuki ; Idani, Naoki ; Ito, Masaru ; Yamasaki, Osamu ; Harada, Norihiro ; Hiramoto, Takanori
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
2010
fDate
22-24 March 2010
Firstpage
198
Lastpage
205
Abstract
Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal perimeter in addition to the pattern density. Dummy fill insertion has been widely adopted to improve the CMP planarity in industrial design flows. However, conventional dummy fill insertion has been derived mainly to optimize the pattern density uniformity, which may worsen the CMP planarity because of missing impacts due to metal perimeter. In this paper, we propose; 1) a design of experiment (DOE) based method of evaluating the quality of fill insertion by using a CMP simulator which considers the impacts due to both pattern density and metal perimeter, and 2) a condition-based dummy fill insertion using the results of the proposed DOE method. Compared to the conventional pattern density driven rule-based fill insertion, the proposed method reduces the post-CMP Cu surface height variation by 24.3%. The metric of the metal perimeter may be applied to the model-based fill insertion methods, which will improve the planarity in the practical fill insertion flow.
Keywords
chemical mechanical polishing; copper; design of experiments; integrated circuit design; CMP predictive models; Cu; ECP predictive models; chemical mechanical polishing-aware design; condition-based dummy fill insertion method; design of experiment based method; industrial design flows; metal perimeter; pattern density driven rule-based fill insertion; pattern density uniformity; post-CMP Cu surface height variation; wafer surface planarity; Approximation algorithms; Chemicals; Integrated circuit interconnections; Laboratories; Manufacturing; Microelectronics; Predictive models; Semiconductor device modeling; Surface topography; US Department of Energy; Chemical Mechanical Polishing (CMP); Design for Manufacturability; Dummy fill;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location
San Jose, CA
ISSN
1948-3287
Print_ISBN
978-1-4244-6454-8
Type
conf
DOI
10.1109/ISQED.2010.5450461
Filename
5450461
Link To Document