DocumentCode
2145228
Title
Reliability studies of a through via silicon stacked module for 3D microsystem packaging
Author
Yoon, Seung Wook ; Witarsa, David ; Lim, Samuel Yak Long ; Ganesh, Vetrivel ; Viswanath, Akella G K ; Chai, Tai Chong ; Navas, Khan O. ; Kripesh, Vaidyanathan
Author_Institution
Inst. of Microelectron., Singapore
fYear
0
fDate
0-0 0
Abstract
In this study, two types of reliability tests are studied for silicon stacked module. One is for temperature cycle solder joint reliability. Another is for drop impact test. Test vehicles are fabricated using silicon fabrication processes such as SiO2 deposition, metal deposition, lithography, through via formation, copper plating and dry or wet etching. After flipchip die and silicon substrate fabrication, they are assembled by flipchip bonder. Daisy chains are formed between flipchip dies and each silicon substrates and resistance measurement is carried out with temperature cycle test (-40/125degC, 2cycles/hr). In case of drop test, the JESD recommended condition B (e.g. 1500 G, 0.5 millisecond duration, and half-sine pulse) is adopted. And in-situ monitoring is carried out to observe the failure during the drop test. Reliability results of through via silicon stacked module indicated that it passed 1000 cycles T/C and survived drop impact test
Keywords
circuit reliability; electron device testing; electronics packaging; flip-chip devices; impact testing; silicon; 3D microsystem packaging; JESD; drop impact test; flipchip bonder; flipchip die fabrication; silicon fabrication processes; silicon stacked module; temperature cycle solder joint reliability; temperature cycle test; Copper; Fabrication; Lithography; Packaging; Silicon; Soldering; Temperature; Testing; Vehicles; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
1-4244-0152-6
Type
conf
DOI
10.1109/ECTC.2006.1645847
Filename
1645847
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