• DocumentCode
    2145829
  • Title

    Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages

  • Author

    Kacker, Karan ; Sidharth ; Dubey, Ajit ; Zhai, Charlie J. ; Blish, Richard C., II

  • Author_Institution
    AMD, Sunnyvale, CA
  • fYear
    0
  • fDate
    0-0 0
  • Abstract
    Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element analysis (FEA) models were used to analyze the effect of underfill height and width on interfacial stresses in a typical organic flip chip package configuration. Peeling and shearing stresses were computed for a large combination of fillet heights and widths (15 times 16 = 240). Three locations of interest: die bottom corner/underfill, die edge/fillet top and fillet bottom/substrate, were studied. For each location, 3D surface plots were generated to depict the variation of shear/peel stress simultaneously with width and height. An analysis of variance (ANOVA) was conducted for the full factorial design of experiments (DOE) to quantify the effect of underfill fillet height and width on the numerically computed shear and peel stresses at each location. Interaction among these variables was permitted and studied, and was found to be significant in some cases. The dominant factor(s) governing interfacial stresses for each location was identified and optimum values recommended. Limited data, with corner fillet heights in the range ~2% to 70% of die thickness, suggested adequate reliability for most field applications. Additional data are required to further validate the results
  • Keywords
    delamination; design of experiments; filling; finite element analysis; flip-chip devices; internal stresses; analysis of variance; design of experiments; finite element analysis; interfacial delamination; organic flip chip packages; peeling stress; shearing stress; underfill fillet geometry; Adhesives; Analysis of variance; Ceramics; Delamination; Flip chip; Geometry; Material properties; Packaging; Stress; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2006. Proceedings. 56th
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    1-4244-0152-6
  • Type

    conf

  • DOI
    10.1109/ECTC.2006.1645871
  • Filename
    1645871