DocumentCode
2146131
Title
Domino gate with modified voltage keeper
Author
Wang, Jinhui ; Wu, Wuchen ; Gong, Na ; Hou, Ligang
Author_Institution
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
fYear
2010
fDate
22-24 March 2010
Firstpage
443
Lastpage
446
Abstract
Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of the strong process parameter variation.
Keywords
logic gates; optimisation; body biased voltage; domino OR gates; modified supply voltage; modified voltage keeper; noise; optimized keeper technique; power efficiency; process parameter variation; speed efficiency; Circuit noise; Crosstalk; Energy consumption; Immune system; Leakage current; Logic arrays; Logic circuits; Low voltage; Noise robustness; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location
San Jose, CA
ISSN
1948-3287
Print_ISBN
978-1-4244-6454-8
Type
conf
DOI
10.1109/ISQED.2010.5450538
Filename
5450538
Link To Document