DocumentCode :
2146428
Title :
Scaling of Stacked gate technology for embedded NVM
Author :
Shum, D. ; Kakoschke, R. ; Strenz, R.
Author_Institution :
Infineon Technol. Dresden GmbH & Co. OHG, Munich, Germany
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
827
Lastpage :
830
Abstract :
Scaling limitations on NVM Stacked gate embedded into high-performance (HP) CMOS logic process will be reviewed with potential solutions identified. As technology continues its shrink path into 65 nm and beyond, scaling is becoming challenged due to the required high fields for write and erase (W/E) in stacked gate technology and the low leakage requirements for long term retention after cycling (RAC) problems. These requirements are imposing fundamental scaling limitations on the cell design as well as dielectrics thicknesses. These challenges require novel innovations to overcome and extend the viability of stacked gate technology to at least the 45 nm node.
Keywords :
CMOS memory circuits; integrated circuit design; NVM stacked gate embedded; cell design; dielectrics thicknesses; high-performance CMOS logic process; retention after cycling problems; size 45 nm; size 65 nm; stacked gate technology; CMOS logic circuits; CMOS process; CMOS technology; Consumer electronics; Costs; Dielectrics; Nonvolatile memory; Technological innovation; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4734670
Filename :
4734670
Link To Document :
بازگشت