An experimental study of integrated DMOS transistors with increased energy capability

Advanced integrated power technologies offer DMOS transistors with substantially reduced sizes. However, a smaller device area increases the thermal impedance, lowering the maximum amount of energy the DMOS can withstand without reaching excessive temperatures and subsequent destruction. Because of this limitation, it is often not possible to fully exploit the very low area specific on-state resistances of modern integrated power technologies. The very high temperatures leading to failure are usually confined to a small region of the DMOS, while most of the active area of the device remains at a much lower temperature. By redistributing the power dissipation from the hotter to the cooler DMOS areas, the peak temperature of the transistor can be lowered without increasing the area. Thus, the device is capable of dissipating larger amounts of energy before destruction. This work presents two different approaches to improve the energy capability of DMOS transistors. Both approaches can be implemented in integrated power technologies solely by layout modifications. No changes of the fabrication process are required. Both approaches are investigated by simulations and measurements to demonstrate their effectiveness.