65nm poly gate etch challenges and solutions

Author

Huang, Yi ; Du, Shan-Shan ; Zhang, Hai-Yang ; Chen, Hai-Hua ; Han, Qiu-Hua ; Chang, Shih-Mou

Author_Institution

Semicond. Manuf. Int. Corp. (SMIC), Shanghai, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1166

Lastpage

1169

Abstract

This paper presents an overview of 65 nm poly gate fabrication challenges emerged during the device performance & yield enhancement on 300 mm wafer. The proposed solutions hinge on the improvement of some critical process parameters in 65 nm gate etch such as, critical dimension uniformity (CDU), through-pitch etch bias (TPEB), line width roughness (LWR) and poly gate profile. More than 7% yield enhancement and improved Vmin (the minimum voltage at which the addressed device function correctly) distribution have been obtained with improved CDU&TPEB.

Keywords

integrated circuit manufacture; integrated circuit yield; critical dimension uniformity; line width roughness; minimum voltage; poly gate etch; poly gate fabrication; poly gate profile; size 300 nm; size 65 nm; through-pitch etch bias; yield enhancement; Etching; Fabrication; Fasteners; ISO; Inspection; Pulp manufacturing; Semiconductor device manufacture; Temperature; US Department of Energy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734745

Filename

4734745