FPGA implementation of a linear systolic array for speech recognition based on HMM

Author

Mosleh, Mohammad ; Setayeshi, Saeed ; Lotfinejad, M. Mehdi ; Mirshekari, Ali

Author_Institution

Dezful Branch, Islamic Azad Univ., Dezful, Iran

Volume

3

fYear

2010

fDate

26-28 Feb. 2010

Firstpage

75

Lastpage

78

Abstract

The history of speech recognition refers to some decades ago. Speech recognition performs by using a number of complicated algorithms. Real-time and rapid execution of these algorithms is very important. In this paper, a linear systolic architecture is proposed which can execute speech recognition algorithms based on Hidden Markov Model (HMM) in parallel and pipeline forms. The proposed architecture is very regular, consisting of a set of identical and simple processor elements, which are connected together locally. In order to evaluate the proposed architecture, it has been designed by using VHDL code and synthesized on FPGA (Vertix2p) running at 320.546 MHZ.

Keywords

field programmable gate arrays; hardware description languages; hidden Markov models; speech recognition; systolic arrays; FPGA implementation; HMM; VHDL code; complicated algorithms; hidden Markov model; linear systolic architecture; linear systolic array; rapid execution; speech recognition; Computer architecture; Decoding; Field programmable gate arrays; Hidden Markov models; History; Pipeline processing; Probability; Speech recognition; Systolic arrays; Viterbi algorithm; FPGA; Hidden Markov Model (HMM); Speech Recognition; Systolic Array;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Automation Engineering (ICCAE), 2010 The 2nd International Conference on

Conference_Location

Singapore

Print_ISBN

978-1-4244-5585-0

Electronic_ISBN

978-1-4244-5586-7

Type

conf

DOI

10.1109/ICCAE.2010.5451202

Filename

5451202