• DocumentCode
    2148680
  • Title

    Dynamic scanning method to clarify the mechanism of WLCSP package reliability issue

  • Author

    Chen, Po-Ying ; Tsai, Chwei-Shyong ; Tsai, Ming-Hsiung ; Kung, Heng-Yu ; Chen, Shen-Li ; Jing, M.H. ; Yeh, Wen-Kuan

  • Author_Institution
    Dept. of Inf. Eng., I-Shou Univ., Kaohsiung, Taiwan
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    1195
  • Lastpage
    1198
  • Abstract
    This study proposes a brand new method for identifying the mechanism that obtains when various current densities are individually applied to the architecture of WLCSP. A multi-steps current-destroying method was applied to clarify the effect of current density and the failure mechanism, both the environments and testing qualifications for these packages are becoming increasingly demanding. Failure mechanisms assumed to have been eliminated, or at least to have been alleviated to some extent in new package technology designs, are once again challenges to their process integrity and reliability. Because of dynamic loading induced by mechanical vibration and impact shock negatively impacting reliability for CSP package, analytical models and simulations of some mechanisms were developed. This work examines the reliability of a wafer-level chip-scale package (WLCSP) subjected to various accelerated current stressing conditions under a fixed ambient temperature of 125°C. A reasonable correlation was obtained between mean-time-to-failure (MTTF) of the WLCSP test vehicle and the average current density carried by a solder joint was obtained.
  • Keywords
    integrated circuit reliability; integrated circuit testing; wafer level packaging; dynamic scanning method; failure mechanism; impact shock; mean-time-to-failure; mechanical vibration; multisteps current-destroying method; process integrity; qualification testing; solder joint; temperature 125 C; wafer-level chip-scale package reliability; Analytical models; Chip scale packaging; Current density; Electric shock; Failure analysis; Qualifications; Testing; Vehicle dynamics; Vibrations; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734761
  • Filename
    4734761