Investigation of low cost consumer electronic system using 1066-Mb/s DDR2 interface design

Low cost is always the favorite feature of consumer electronics. The purpose of this paper is to study the possibility of low-cost design for DDR2-1066 memory interface. The S-parameters simulations of the PCB, DDR2 controller and SDRAM packages were performed using the electromagnetic field solvers up to 3 GHz. Those broadband S-parameters were integrated with the chip SPICE models in the SPICE simulator for transient analyses. The results indicated that DDR2 command and control routing topology with zero series termination on the PCB and the controller using Level-7 drive strength encapsulated in the 2-layer PBGA package achieved 915-ps eye-aperture time, 507-ps signal skew, 2.14-V overshoot, and -0.37-V undershoot.