Title :
Optimal design of low power nested GM-C compensation amplifiers using a current-based MOS transistor model
Author :
Xie, X. ; Schneider, M.C. ; Embabi, S.H.K. ; Sanchez-Sinencio, E.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
31 May-3 Jun 1998
Abstract :
A sound design of low power multistage amplifiers is presented. The amplifiers are stabilized by Nested Transconductance-Capacitance Compensation (NGCC). The key for an optimal design is a current-based MOSFET transistor model, which allows the amplifiers to be designed in moderate inversion. With 2 V supply voltage and 10 kΩ/20 pF load, a four-stage amplifier implemented in a 1.2 μm n-well CMOS process achieved 1.03 MHz gain bandwidth product, 103 dB open loop gain and 62.7° phase margin with a power consumption of 0.3 mW. The active area of the amplifier is 0.0052 mm2. With the same specifications, a three-stage amplifier was also integrated in the 1.2 μm n-well CMOS process. Compared to the design in strong inversion, both amplifiers satisfy the specifications while the power consumption is reduced by a factor of 3
Keywords :
CMOS analogue integrated circuits; circuit optimisation; compensation; integrated circuit modelling; operational amplifiers; 0.3 mW; 1.2 micron; 103 dB; 2 V; NGCC amplifier; active area; current-based MOS transistor model; gain bandwidth product; low power multistage amplifier; n-well CMOS process; nested transconductance-capacitance compensation amplifier; open loop gain; optimal design; phase margin; power consumption; CMOS process; Capacitors; Energy consumption; Frequency; Low voltage; MOSFET circuits; Poles and zeros; Power amplifiers; Topology; Transfer functions;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706804
