The impact of interface quality on High-K gate dielectric devices for 32 nm technology and beyond

Future devices will be fabricated with high-k/metal gate stack and possibly employ 3D devices and/or high mobility channel materials. Gate stack research targeted for devices scaled to 32 nm and beyond should address the compatibility with scaled CMOS technologies in addition to the EOT scaling of High-K dielectric itself. This paper discusses recent progress and challenges in high-k dielectric for scaled CMOS technologies, especially the impact of the robustness of the interfacial layer beneath the high-K bulk on the MOSFET threshold voltage roll-off and the device reliability such as stress-induced leakage current (SILC). The directions to improve the interfacial quality of HK/MG stack will be discussed. Challenges of high-K dielectric formation targeted for future SiGe channel devices will be highlighted.