Why are SCE overestimated in FD-SOI MOSFETs?

Experimental results show that the measurement and interpretation of short-channel effects (SCE) are misleading in advanced SOI MOSFETs. Part of SCE is due to the parasitic contribution of the back gate via channel coupling. We demonstrate that the contributions of each gate to the overall SCE can be discriminated. Numerical simulations indicate that their mutual relevance depends on the transistor architecture. A pragmatic biasing method is proposed for the reduction of charge sharing and DIBL effects. We present a simple model which is effective in decorrelating the genuine SCE at each gate and can be advantageously applied to device optimization.