A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technology

This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250 kHz channel hopping. Measurement results are given. Mixer achieves -8dBm P1 dB and 6.25 dB noise figure, phase noise of PLL is -127 dBc/Hz @ 1 MHz offset and settling time of channel hopping is within 30 μs. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13 mm², and draws 75 mA for 1.8 V supply voltage.