• DocumentCode
    2151925
  • Title

    IC for neural signal regeneration

  • Author

    Wenyuan Li ; Zhigong Wang

  • Author_Institution
    Inst. of RF-& OE-ICs, Southeast Univ., Nanjing, China
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    1749
  • Lastpage
    1752
  • Abstract
    Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC¿s 0.6 ¿m CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function electrical stimulation (FES) stage. The neural signal detecting circuit amplifies the detected weak signal come from the electrode to such a voltage that the FES circuit can be driven appropriately. The FES circuit amplifies the signal further so that the neural signal can be regenerated through the stimulating electrode. The neural signal regenerating IC occupies a die area of 2.82 mm×2.00 mm. Under double supply voltages of ±2.5 V, the DC power consumption is less than 50 mW. The on-wafer measurement results are as follows: the output resistor is 118 m¿, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 dB to 90 dB. The circuit has been used for in-vivo experiments on the rat¿s sciatic nerve as well as spinal cord with the cuff type electrode array or a needle twin-electrode, and the neural signal has been regenerated successfully both on a rat¿s sciatic nerve bundle and on a spinal cord.
  • Keywords
    bioelectric phenomena; signal generators; CMOS technology; DC power consumption; adjustable gain; buffer stage; discrete devices; function electrical stimulation; neural signal amplifier; neural signal regeneration; on-wafer measurement; CMOS integrated circuits; CMOS technology; Electrodes; Integrated circuit technology; Rabbits; Rats; Signal design; Signal detection; Spinal cord; Voltage; CMOS; FES; IC; Neural Signal Regeneration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734892
  • Filename
    4734892