A novel architecture for VLSI implementation of RSA cryptosystem

The RSA system is widely employed in networking applications and achieves good performance and high security. In this paper, we use Verilog to implement a 16-bit RSA block cipher system. The whole implementation includes three parts: key generation, encryption and decryption process. The key generation stage aims to generate a pair of public key and private key, and then the private key will be distributed to receiver according to certain key distribution schemes. The memory usage and overhead associated with the key generation is eliminated by the proposed system model. The cipher text can be decrypted at receiver side by RSA secret key. These are simulated in Xilinx and hardware is synthesized using RTL Compiler. The existing and proposed models are then analyzed for performance measures using Synopsis-Design Vision. Net list generated from RTL Compiler will be used to generate IC layout.