Low power design of column readout stage for large format IR ROIC

A novel column readout architecture for large format snapshot infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 4 M Hz, by applying stand-by and the technology of output bus pre-settling, the power of the column readout stage has been reduced from 6.4 mw to 0.8 mw, which reduced more than 85% In the output bus pre-settling readout structure, ROIC has four output buses totally and drive the output buffer alternately. When one output bus is being read out, the other three are preparing their data. After the column select signal arrives, output bus has no SR process but small signal settling process, which helps to reduce CSA¿s bandwidth and power. A 384×288 IR ROIC with pixel size of 30×30 ¿m² has been designed with this architecture which based on CSMC 0.5 ¿m DPTM n-well CMOS process.