Design and analysis of on-chip router

Network-on-chip (NoC), one of the most promising interconnection schemes for complex SoC design, presents large design space. Because the influence of different parameters on the performance of the NoC varies significantly, it is desirable to analyze and understand specific effect of these parameters on the overall performance in order to provide NoC designers guidelines to optimize their plans. In this paper, we mainly focus on the router design parameters on both system level including traffic pattern, network topology and routing algorithm, and architecture level including arbitration algorithm and buffer mechanism. At last, we analyze the resource consumption of the router and propose possible approaches to reduce the cost.