DocumentCode
2153992
Title
Process-design co-optimization for FPGA
Author
Xiang, Qi
Author_Institution
Altera Corp., San Jose, CA, USA
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
2039
Lastpage
2042
Abstract
Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges, process-design co-optimization is required. With co-optimization of process, circuit, and architecture, 45% static power reduction is achieved for a 40 nm FPGA design. With optimized analog devices, high data rate (8.5 Gbps) transceivers are produced using a 40 nm digital process.
Keywords
field programmable gate arrays; logic design; optimisation; transceivers; FPGA process-design co-optimization; digital process; field programmable gate array; high speed transceiver I/O demand; power management; size 40 nm; static power reduction; Energy consumption; Energy management; Field programmable gate arrays; Geometry; Integrated circuit technology; Leakage current; Logic; Moore´s Law; Transceivers; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734973
Filename
4734973
Link To Document