A novel linear histogram BIST for ADC

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC¿s static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.