Title :
On zero clock skew hold time failure in scan test
Author :
Zhang, Xiaonan ; Bai, Xiaoliang ; Laisne, Michael ; Matar, Charlie
Author_Institution :
Qualcomm, Inc., San Diego, CA, USA
Abstract :
This paper studies a new hold time failure mode found in deep sub-micron low power CMOS production scan testing. The root causes of failure are discovered and duplicated in simulations. Vccmin of scan chain integrity is defined and studied for the first time. Solutions for enhancing scan chain integrity are proposed.
Keywords :
CMOS integrated circuits; integrated circuit testing; deep sub-micron low power CMOS production scan testing; hold time failure mode; scan chain integrity; zero clock skew; Clocks; Power supplies; Production; Profitability; Robustness; System testing; System-on-a-chip; Time to market; Voltage; Zero current switching; Scan test failure; Vccmin; hold time failure; process local variability; scan flop design;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734984
