Title :
A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate
Author :
Hashemi, SayedMasoud ; Razavi, Behzad
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. Realized in 65-nm CMOS technology and sampling at 1 GHz, the prototype exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1-V supply.
Keywords :
CMOS integrated circuits; UHF amplifiers; analogue-digital conversion; calibration; digital-analogue conversion; pipeline arithmetic; CMOS technology; Nyquist rate; SNDR; calibration; double-sampling residue amplifier; frequency 1 GHz; interleaved precharged DAC; power 7.1 mW; residue gain error; size 65 nm; two-stage pipelined ADC; voltage 1 V; CMOS integrated circuits; Calibration; Clocks; Frequency measurement; Noise; Prototypes; Resistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
DOI :
10.1109/CICC.2013.6658421
