Title :
A novel packing algorithm for sparse crossbar FPGA architectures
Author :
Wang, Kanwen ; Yang, Meng ; Wang, Lingli ; Zhou, Xuegong ; Tong, Jiarong
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results show that half populated crossbar FPGA architecture achieves 7% area improvement compared to fully populated counterpart with only 3% number of external nets overhead.
Keywords :
electronics packaging; field programmable gate arrays; CAD flow; cluster-based FPGA; connection gain function; direct graph searching method; logic elements packing; packing algorithm; sparse crossbar FPGA architectures; Capacitance; Clustering algorithms; Delay; Feedback; Field programmable gate arrays; Logic design; Multiplexing; Routing; Switches; Timing;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4735050