A novel OTA-based fast lock PLL

This paper describes a novel fast lock scheme for phase-locked loops (PLLs). The proposed scheme uses a simple operational transconductance amplifier (OTA) to achieve significant reduction in PLL lock acquisition time without affecting PLL noise performance. The new scheme allows short starting time and fast dynamic power cycling for various subsystems on SOC´s. Multiple PLLs utilizing the new fast lock schemes were implemented in multi-port SRAM chip to provide frequencies from 400MHz to 1.6GHz, The chip was fabricated using 65nm CMOS process. Silicon measurements across corner lots show significant reduction in PLL lock time, by a factor of 6.5X, over device operating conditions.