DocumentCode :
2157402
Title :
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator
Author :
Iizuka, Tetsuya ; Someya, Takao ; Nakura, Toru ; Asada, Kunihiro
Author_Institution :
Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
fYear :
2013
fDate :
22-25 Sept. 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a time-domain analog signal hold-and-replication circuit which holds an input time interval of two signal transitions and replicates it any number of times. The proposed Time Difference Hold-and-Replication (TDHR) circuit utilizes a dual pulse ring oscillator to hold the input time interval without any time deterioration due to mismatches. The proposed TDHR circuit is implemented in a 65nm standard CMOS technology only with digital cells in the standard-cell library. It realizes 100ps to 1.2ns time interval hold and replication with the maximum error of ±50ps and consumes 0.51mW while occupying 40×60μm2 area. This TDHR circuit is also used for an input time amplification and a TDC resolution enhancement application of the proposed TDHR is also demonstrated in this paper.
Keywords :
CMOS digital integrated circuits; analogue circuits; oscillators; time-domain analysis; CMOS technology; TDC resolution enhancement application; TDHR circuit; all-digital time difference hold-and-replication circuit; digital cells; dual pulse ring oscillator; input time amplification; input time interval; signal transitions; size 65 nm; standard-cell library; time 100 ps to 1.2 ns; time-domain analog signal hold-and-replication circuit; CMOS integrated circuits; Delays; Ring oscillators; Time-domain analysis; Tin; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location :
San Jose, CA
Type :
conf
DOI :
10.1109/CICC.2013.6658510
Filename :
6658510
Link To Document :
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