142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process

Author

Naiknaware, Ravindranath ; Fiez, T.S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

fYear

2000

fDate

2000

Firstpage

5

Lastpage

8

Abstract

A ΔΣ ADC designed in a 0.6 μm CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 kΩ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply

Keywords

CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; integrated circuit noise; ΔΣ ADC; 0.6 micron; 1 V; 100 to 1000 Hz; 22.8 mW; 3 V; CMOS process; biomedical devices; delta-sigma ADC; high resolution converter; noise cancellation strategy; noise reduction mechanism; power optimized ADC; reference voltage; remote seismic monitoring; sensitive instrumentation; Bandwidth; Biomedical monitoring; CMOS process; Dynamic range; Instruments; Noise cancellation; Noise reduction; Remote monitoring; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852606

Filename

852606