Defect-tolerant implementation of a systolic array for two-dimensional convolution

A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural concepts for the design of large-area chips have been investigated and applied to the chip-design. Yield calculations show that, by the combination of new architectural concepts, effective hierarchical reconfiguration schemes, layout redundancies, and design of global parts using conservative design-rules, a high yield increase (67%) with low area overhead (6%) has been achieved