Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience

Author

You, Eileen ; Choe, Swee Yew ; Kim, Chin ; Varadadesikan, Lakshminarasimh ; Aingaran, Kathirgamar ; MacDonald, John

Author_Institution

Sun Microsyst. Inc., Palo Alto, CA, USA

fYear

2000

fDate

2000

Firstpage

491

Lastpage

494

Abstract

This paper discusses accuracy issues in parasitic extraction for the design of multimillion-transistor integrated circuits. The methodology reported aims at reducing the gap between the parasitic values estimated during implementation and the results of post-layout extraction. The objective is to obtain progressively refined interconnect models in hierarchical design flows. This methodology was developed for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses

Keywords

integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; microprocessor chips; timing; 800 MHz; UltraSPARC-III microprocessor; design experience; extraction methodology; hierarchical design flows; interconnect modeling; multimillion-transistor integrated circuits; noise analysis; parasitic extraction; parasitic values; post-layout extraction; progressively refined interconnect models; timing analysis; Circuit simulation; Crosstalk; Data mining; Design methodology; Integrated circuit interconnections; Microprocessors; Parasitic capacitance; Performance analysis; Signal analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5809-0

Type

conf

DOI

10.1109/CICC.2000.852715

Filename

852715