Testability considerations

Single-fault, multi-fault, 0-1 static sensitizable path, and robust path delay fault are often used to measure the testability of a circuit. We explore the relationships among these testabilities. In addition to the relationships discovered before, we prove that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We also prove that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further prove that the three transformations D_1,1,2 (J. Rajski and J. Vasudevamurthy, 1992), extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We answer the following two open questions: does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?