DocumentCode
2160441
Title
Capturing synchronization specifications for sequential compositions
Author
Zhu, Zheng ; Johnson, Steven D.
Author_Institution
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
fYear
1994
fDate
10-12 Oct 1994
Firstpage
117
Lastpage
121
Abstract
We explore the problem of adding synchronization information to high-level system specifications. At this level of specification the components of a system may follow non-trivial, but implicitly specified sequential protocol in order to perform their operations. We illustrate a method of extracting protocols for closely coupled systems of such components. A language is defined for specifying external timing and behavior. Although limited in its expressiveness, this language allows us to derive partial synchronization conditions in the form of timing inequalities. The solution to a system of timing inequalities is itself a timing expression, from which a controlling state-machine can be synthesized
Keywords
finite automata; finite state machines; sequential machines; synchronisation; protocols; sequential compositions; state-machine; synchronization specifications; system specifications; timing inequalities; Computer science; DH-HEMTs; Digital circuits; Fires; Hardware; Protocols; Specification languages; Tellurium; Timing; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-6565-3
Type
conf
DOI
10.1109/ICCD.1994.331868
Filename
331868
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